Sub-nano ampere current references are of increased interest recently, as micro-scale sensor nodes and bio-implantable systems with limited power budgets gain popularity. These systems use ultra-low-power mixed signal circuits such as oscillators and analog amplifiers, which require current references with low power overhead as key building blocks.
To motivate the need for an ultra-low power current reference with low temperature dependence, consider a recently reported 65 nW CMOS temperature sensor. This sensor uses multiple subthreshold-mode operational amplifiers, each of which consumes 100 s of pA. The amplifiers make up 6% of total analog front-end power consumption at room temperature. However, due to the lack of a temperature-compensated current reference, amplifier power increases exponentially with temperature such that they consume 52% of total analog front end power at 100° C. Adopting the current reference circuit proposed in this disclosure would limit the amplifier and current reference overhead power to only 6% at 100° C., reducing total analog front-end power from 56.2 nW to 14.9 nW at 100° C.
Many conventional current reference circuits are variations of the β-multiplier reference shown in FIG. 1A. However, this type of reference is unsuitable for the sub-nA current generation as it requires an extremely large resistor of 1 GΩ or more. Further, a start-up circuit is needed to prevent the circuit from becoming trapped in an undesired operating point, adding area overhead. One known technique replaces the resistor with a MOSFET to create a subthreshold version of the β-multiplier, however the circuit remains in the nW range (88 nW@1.3V).
With reference to FIG. 1B, other proposed current references employ a reference voltage and a resistor, achieving a temperature coefficient (TC) as low as 24.9 ppm/° C. However, those circuits consume μW's and their use of resistors complicate sub-nA current generation. Also, polysilicon resistors vary by up to ±25%; this variability is independent of transistor process variation, potentially worsening process sensitivity.
This disclosure proposes a new topology to generate a sub-nA (20 pA) level reference current with very low power overhead. It shows 780 ppm/° C. TC and consumes 23 pW, which is more than fifty times smaller than the lowest power consumption reported previously. This disclosure also describes techniques to improve supply voltage regulation and load voltage regulation.
This section provides background information related to the present disclosure which is not necessarily prior art.